Digital Architect

Snowcap is building a large-scale digital compute system on superconducting PCL logic. The architecture for that system does not exist anywhere — not in textbooks, not in prior product, not at any other company. CMOS reference designs do not transfer cleanly because the logic family, clocking, interconnect, and energy model are all different from the ground up. This role owns the architecture from the top.
You will define the top-level chip architecture: system partitioning, clocking strategy, interconnect hierarchy, I/O, and the test strategy that flows out of those choices. You will work directly with physics leads to translate Josephson junction and PCL device constraints into architectural requirements, and you will hand a clean microarchitecture specification to the Digital Microarchitect. We are a flat, matrixed organization — there is no architecture committee, no review board between you and the decision.
In twelve months, the architecture document you produce should be the single source the rest of the chip team — RTL, verification, physical design, test — reasons from. It should be defensible against physics, buildable in the fab capability we have, and testable with the lab we are standing up. That is the bar.

- Own the top-level architecture specification for Snowcap's PCL digital chips — system partitioning, block hierarchy, and the document the rest of the team builds from.
- Define the clocking strategy for a non-CMOS logic family where conventional synchronous design assumptions do not apply.
- Design the on-chip interconnect hierarchy and I/O architecture, including the cryogenic-to-room-temperature boundary that no CMOS reference design has to think about.
- Establish the chip's test strategy and test protocol at the architectural level — what is observable, what is controllable, what gets verified where, and what the lab has to be able to measure.
- Partner with physics leads to translate Josephson junction and PCL device behavior into architectural constraints and budgets — and push back when an architectural choice asks more from the device than the physics will deliver.
- Drive the architecture-to-microarchitecture handoff: produce the specification, defend it under review, and revise it when downstream work surfaces a real problem.
- Make the compute/memory/interconnect tradeoffs that determine what workloads this system is good at — with AI inference and HPC-class workloads as the primary lens.
- Set the standards for what an architecture specification at Snowcap looks like — clarity, completeness, and the kind of rigor that downstream RTL, verification, and test engineers can actually rely on.

- Lead or principal architect on a production digital chip program — CPU, GPU, TPU, NPU, or similar — where your architectural decisions shipped in silicon that real workloads ran on.
- Demonstrated ability to reason from first-principles device physics constraints up to system-level architecture. PCL design space requires this; conventional CMOS architects who treat the device as a fixed primitive will not be effective here.
- Track record of writing the architecture specification — not just contributing to one. The document, the rationale, the tradeoffs, and the defense of the choices.
- Deep, working understanding of clocking, interconnect, and I/O architecture at modern compute scale — and the judgment to know which of those assumptions break in a non-CMOS logic family.
- Experience setting architectural test strategy and DFT direction, not just leaving it to the back-end team to figure out.
- Comfort operating with significant ambiguity at the earliest stages of a design, in a startup environment with no architecture playbook to inherit.

- Architecture work on AI inference accelerators — TPU-class, NPU-class, or comparable dataflow/tile-based machines — and a working understanding of the compute/memory tradeoffs that govern them.
- Experience defining architecture in a non-standard logic family, asynchronous design, wave-pipelined systems, or any environment where conventional synchronous CMOS assumptions had to be re-derived.
- Background in HPC chip architecture, vector/matrix engines, or large-scale interconnect design at the system level.
- Familiarity with superconducting digital logic — PCL, SFQ, AQFP, RSFQ, or related families — at any level of depth. We do not expect this. We will weight it heavily when we find it.
- Published architecture work, patents, or shipped products where the architectural rationale is visible and defensible.
- Evidence of cross-disciplinary fluency — circuits, devices, software, workload analysis — that lets you bridge the conversations between physics, RTL, and the workloads the chip is meant to run.
- Mentorship or technical leadership track record with downstream microarchitecture and design teams.

Snowcap is a small, technically elite team doing chip architecture that has never been attempted at commercial scale. There is no internal reference design, no prior tape-out to study, and no architecture team above you to defer to. You are the architecture team. You will write the spec, defend it under physics pushback, and revise it when the data argues back.
We are a flat, matrixed organization. You will work daily with physics leads, microarchitecture, verification, physical design, and test — directly, without layers. Decisions that take quarters at a large semiconductor company will take days here, and the tradeoff is that the decisions are yours and the consequences are visible.
This role is on-site at our San Francisco Bay Area or Jacksonville Metro location. The work is hands-on at the whiteboard, in the spec, and in conversation with the people building the silicon. If you need a mature architecture organization with established review cadences and a chain of senior architects to escalate to, this is not the right fit. If you have been waiting for a clean sheet on a real problem, you are in the right place.

Snowcap builds superconducting compute. (Edit in admin.)

Full medical, dental, and vision · 401(k) · Relocation assistance available for candidates outside the area.
Base salary range is shown in USD, posted in good faith and in compliance with California pay transparency law (SB 1162). Actual offer depends on experience, skills, and location, and is exclusive of equity, bonus, and benefits. Range reflects the San Francisco Bay Area market; offers for the same role based in Jacksonville Metro, FL are typically 15–25% lower in line with local market norms.
Based in the San Francisco Bay Area or Jacksonville Metro, FL · On-Site.

Snowcap is an equal opportunity employer. We do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other protected characteristic. (Edit in admin.)